Part 1 - Starting Cadence

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1. Running Cadence

Open a new terminal window. Switch to the c-shell, go to your working directory and run IC 5.1.41 by typing:

cd cdscad
icfb&

the "&" lets you keep using the terminal to perform other tasks while ifcb is still running.

2. Tour

Now that Cadence has finished loading you should see three windows. The smallest of these says

'Done loading NCSU_CDK customizations.'

indicating that the design kit is properly installed. This window is called the CIW. It is the main control window for Cadence. You can type commands in the command line or use the mouse to select commands from the toolbar.

The second window says

"what's new in 5.1.41"

Close this window.

The last window that is currently open is the Library Manager. The library manager allows you to navigate through the hierarchy of items that you will create as you use cadence. These items will include libraries, cells, and cellviews. Now is probably a good time to discuss hierarchical design.

Hierarchical design is what makes CAD so powerful. You can design small parts called cells and easily reuse those parts many times to create a larger object. Then you can reuse this larger object as a cell in an even larger object and so on. A properly designed hierarchy will save you tons of time, it will be easy to understand, and easy to modify if needed.

There are many ways to organize a hierarchy and you can decide what works for you, but the most logical to me is to make each physical object in the design a cell, thus a transistor is a cell. Multiple transistors will be used to make gate cells. Multiple gates will make circuit cells, like adders or multipliers. These will ultimately be combined to make a core cell (all the guts of your chip) and this will be plugged into the pad-frame cell to make your final layout.

Well designed cells will plug together nicely without a lot of modification. Basically if you ever have to draw the same thing twice, it should have been a cell.

3. Creating a New Library

Create a new library by selecting File->New->Library from the library manager window. Name your new library 'EE425'.

A pop up will ask you if about a technology file.

Select "Attach to an existing techfile" and click OK.  Select the proper techfile from the drop-down menu and click OK. In our case this is "NCSU_Techlib_AMI06".

This will set up the layers you draw to correspond with the various fabrication steps that the foundry uses to make your chip. It will also tell the program what models to use when simulating your circuits.

Part 2 - Schematic Capture

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Overview

In this module you will create a schematic for a CMOS inverter.

Creating a New Cellview

Each cell will have several views. These include schematic, symbol, layout, extracted, and potentially some others. Each view contains information about a different aspect of the object or its behavior.

In the Library Manager window, highlight your newly created library and select File->New->Cellview

A create file dialog box will appear. Enter "inv" in the Cell Name field. Make sure that the View Name reads "schematic" and the Tool drop-down reads "Composer-Schematic". Click OK

The Virtuoso Window will open. Virtuoso is the tool that is used for drawing schematics and layouts.

Selecting and Placing Components

In the virtuoso window, select Add->Instance. This will open the component browser. You can also just hit the 'i' key to call the instance command. Select "NCSU-Analog Parts" from the library drop-down. Browse through the available parts to find Pmos4. When you select it, the Add Instance window will open as shown below.


The top portion of the window should already be set to point to the Pmos4 cell, since you selected it with the component browser but if you change your mind, you can type in a new component name or browse for a different component.

The pmos4 is an example of a parameterized cell. P-cells have a variety of parameters that can be set when they are instanced and can also be changed later. Right now, the only parameter we will worry about are length and width. These are the phyiscal gate length and gate width of the transistor. These values are constrained by the design rules that the MOSIS sets for each process. By default, they are set to the minimum allowable value right now, so this is the smallest transistor you can fabricate on your chip. We'll leave it that way for now.

Select the virtuoso window and you will see the highlighted outline of a transistor. Click once to place one instance of the pmos4. Now return to the add Instance window, select nmos4 and add one instance of nmos4 as well. The location is not important since we can move them around later. You can move an instance by clicking it to select it and then using the move icon on the left toolbar, or hitting the 'm' key.

Wiring it Up

Position the transistors so that the pmos is above the nmos (remember, the pmos form the pull-up network, and the nmos form the pull-down network.) Now you will add wire to connect the components. Select the wire tool from the left toolbar. Wire the two transistors together to form an inverter. Don't forget to connect the body terminals to the supplies. Your circuit should look something like this:

Adding Pins

Now we need to add pins so we can get signals into and out of our circuit. In the virtuoso window select Add->Pin. The add pin dialog will pop up. Name the pin 'in' and select type inputOutput. Now place the pin on the schematic. Repeat this for the other pins 'out' 'vss' and 'vdd.' Once you have the pins in place, wire them up with the wire tool. You should get something like this:

Finishing

Select Design->Check and Save. Check the CIW window to see if you have any errors. If not, close virtuoso, you are done capturing your schematic.

Part 3 - Symbol Creation

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Overview

In this module you will create a symbol for your CMOS inverter.

Making the Symbol Cellview

Open the schematic for your inverter cell. In Virtuoso, select Design->Create Cellview->From Cellview. The following window will open.

Be sure the settings are exactly like the image. Click OK and a symbol options dialog will appear. Specify where you want the pins to appear in the symbol. Since we want to draw the typical inverter symbol we will put the in pin on the left, out on the right, vdd on top an vss at the bottom. Click OK and a symbol will be drawn for you.

Editing the Symbol

This is the generic symbol which you will want to change. Drag the pins and lines around with the drawing tools to get a symbol that you like. You can highlight and delete the parameter labels. We didn't give our cell any parameters so these aren't useful. You final symbol should look something like this.

Part 4 - Test Bench Creation

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Overview

In this module you will create a testbench circuit for your CMOS inverter.

Make the Testbench cell

Using the library manager, make a library called EE425_Test. This is where you will put the testbench schematics for all your cells. That way you can keep them separate from the cells you will actually use in your design. Its not that important, just a bit of housekeeping. Create a new schematic cellview called inv_test.

Placing the Components

Add an instance of your inv cell. You will see the symbol that you drew with the pins and pin names. Now you want to add some voltage sources. In the NCSU Analog Parts library you will find a cell called vdc. As the name suggests, this is a DC voltage source. Add two of these to the schematic. Also find a capacitor to serve as a load and add one of those. Finally, instance a gnd symbol from the same library. Wire it up like this:



Click on the voltage supply that connects the vdd and vss. Click the properties button on the toolbar and set the DC voltage to 5 volts. The other supply will provide the input for our simulation so leave it as is for now.

Check and Save your circuit.

Part 5 - Schematic Simulation

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Overview

In this module you will perform DC and Transient analyses of your inverter using the testbench circuit.

Starting the Analog Environment.

From the Virtuoso window, select Tools->Analog Environment. You will see this window appear.



This is the main simulation tool in Cadence. It allows you to perform a wide variety of simulations useing several different types of modeling tools. Right now we'll be using SpectreS which is a solver similar to Spice. Later on, we may use some other types of solvers which will be faster for very complex circuits.

Setting up the DC simulation

Select Setup->Design, and verify that the correct cell is selected.
Select Setup->Simulator/Host/Directory and make sure SpectreS is selected as the simulator.
Select Analyses->Choose

This will bring up a dialog with various analyses that you can perform. Select DC and make sure enable is selected. Under the sweep variable, select component parameter. Click select component and returning to the schematic window, click on the DC voltage source at the input of the inverter. A new window should open asking which parameter you want to sweep. Select DC Voltage. Back in the Analyses window, enter the start and stop values to be 0 and 5 volts, set the sweep type to linear and enter that you want 50 points.

Select Outputs->To Be Plotted->Select on Schematic.

Click on the nets that you would like to plot. Select the nets that include the input and output of the inverter.

Running the DC simulation

Click the green traffic light button to run the simulation. Click the plot button to plot the results.
You will see the DC response of circuit. The input voltage is plotted on the x-axis and the output voltage is plotted on the y-axis. You will notice that the response is not quite symmetric. This is due to the fact that the n and p devices have different characteristics. Recall that we made both devices the minimum size in our schematic. We could now go back and adjust these sizes to get better performance. Since the transistors are parametrized cells, we could even hold the voltage constant and sweep the size of one of the transistors to determine the optimal size.



You can save your plot by selecting File->Save as image.

Setting up a Transient Simulation

Now we will edit our testbench schematic to do a transient analysis of the inverter circuit. In this case we will use a pulse generator as the input. We can measure the output as we adjust the frequency or the load.

Return to your schematic and replace the 'vdc' DC source driving the input of the inverter with a 'vpulse' source. Set V1 and V2 to 0 and 5 volts respectively and set the pulsewidth and period to 1ns and 2ns respectively. Note that when entering values into cadence, you enter the prefix but not the units (type '1n', not '1ns') This will give us a 5 volt square wave at 500MHz. Check and Save your file.

Running the Transient Simulation

Open analog environment and select Analyses->Choose

Select tran and set the stop time to 10ns. We will observe the device over multiple periods to ensure that it behaves consistently.

Now select the outputs to plot as you did before. Run the simulation. You should see this:



Now, go back and adjust the load capacitor or the pulse frequency and see what happens to your waveform. What is the fastest you can drive this circuit?

Part 6 - Layout Creation

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Overview

Now that we have designed a circuit and convinced ourselves that it should work, we actually want to implement this circuit in silicon. That requires us to create a physical layout for the circuit. This physical layout will be used to generate the mask set used to fabricate the circuit on a silicon wafer. There are a variety ways to go from a schematic to a physical layout. These range from full-custom hand layout where every single transistor and wire is drawn by hand to fully-synthesized layouts which are entirely computer generated. Most designers use something in between. In order to learn as much as possible we will do the entire design by hand. This isn't as bad as it sounds as long as you use good hierarchical design principles.

Getting Started

We will create a new Cell View for our layout. Open the library manager, select your EE425 library then select File->New->Cell View. Enter 'layout' for the cell view name and Virtuoso for the tool. Click ok.

The virtuoso window will appear and will look similar to the one you used for drawing schematics and symbols, however, there will be another new window, called the LSW (layer selection window.) This window lists all the available layers for the process you have selected. It also allows you to select the current layer for drawing as well as to choose which layers to display or to protect.

Drawing the PMOS

We will start laying out our circuit by drawing the PMOS. It is slightly more complicated than the NMOS so we'll do it together and then you can do the NMOS on your own.

Active (Diffusion)
The first step is to draw the p-type diffusion (or active) region. This will define the source and drain regions of the transistor and well as the width of the channel. Recall that our PMOS had a width of 1.6um. Select pactive from the LSW, and use the rectangle tool (near the botton of the lefthand toolbar) to draw a rectangle that is 3.6um wide and 1.5um high. The location is not important as we will move it around later.

Notice that you can only move the mouse by increments of 0.15um. This is not an accident. For the current process, AMI06, lambda is 0.3um. So 0.15 corresponds to 1/2 lambda. This increment is called the design grid or manufacturing grid and is the minimum address size of features on your masks. So even though the smallest feature you can draw is 0.6um or 2 lambda, you can position these features with a precision of 0.15 um.

Gate Poly
Now we will draw the gate of the transistor. Select Poly from the LSW. Draw a rectangle that is 0.6um wide and 2.7um high, centered at the same point as the active region. Wherever poly crosses active will form the channel of a transistor.

Here's what you should have now:



Hint: To zoom in press ctrl-z, to zoom out press shift-z. Use arrow keys to move the view around.

Active Contacts
Now we will contact the active region to form the source and drain of the PMOS. Select layer 'cc' from the LSW. Don't ask me why they named this layer 'cc' I don't know. 'cc' allows you to form a contact between active or poly and the first metal layer, 'metal1.' Draw two rectangles that are 0.6um by 0.6um (2 lambda x 2 lambda) to form source and drain contacts as shown:



Hint: You could have used the copy function to make the second rectangle. Highlight an object or multiple objects, press 'c' and then point to the destination and click. Also, try out the ruler function. It's the last button of the toolbar.

Metal
Let's draw the metal layer that will contact the diffusion layer through the contacts we just drew. Select 'metal1' from the LSW. Draw two rectangles that surround the contacts by at least 0.3um or 1 lambda. Typically they would be the same width as the active region but they don't have to be. Draw them as shown for now:



P Select
The active layer tells the foundry where to perform ion implantation, but not what type of dopant to use. That information is conferred through the layers 'pselect' and 'nselect' You might have thought that the name 'pactive' implied that this was the p-diffusion region and that 'nactive' implied n-diffusion, but actually both these layers share the same layer number and get converted to a single layer 'active'. In fact, you could have used active in place of pactive or nactive and the result would be the same. They are just there for convenience (they help you remember which flavor of MOS you are working with.

Select layer 'pselect' from the LSW. Draw a rectangle that surrounds the pactive by 2 lambda(0.6um) in all directions as shown:



N-Well
The PMOS transistors must sit in an n-type diffusion well to isolate them from the p-type substrate. Select 'nwell' from the LSW and draw a rectangle of width 7.8um and height 5.1um as shown.



You may wonder why the well is not centered with respect to the PMOS. This is where we are going to put the well tap. The well tap allows us to contact the n-well and ensure that the pn junction formed by the active region and the well remains reverse-biased, electrically isolating the transistor.

Well Tap
Now we are going to draw the well tap. This consists of an n-type diffusion region (nactive and nselect) and a contact.

First we need to use the stretch command to edit one of the rectangles we already drew. hit 's' and select the edge that you wish to stretch, then click on the destination. Move the left edge of the pselect rectangle 0.6 um to the right.

Now select 'nselect' from the LSW and draw a rectangle that abuts the 'pselect' with a width of 2.1um and a height of 2.7um.

Select 'nactive' and draw a 1.5um square abutting the 'pactive' region.

Finally, using 'cc' draw a 0.6um square contact in the 'nactive' region. It should be a distance of 2 lambda from the adjacent p diffusion region. Stretch the metal layer covering the left contact so that it also covers the well tap. This will tie the well to the drain of the pmos. You just finished drawing your first transistor.

Here is what the completed PMOS with the well tap should look like.

Drawing the NMOS

I expect that you can do most of this on your own now so I'll just give you a few hints. Most of the rectangles will be the same size for the nmos as for the pmos since the design rules don't specify which type of doping they refer to.

Active (Diffusion)
This time we will use 'nactive' to draw the n-type diffusion region, although, recall that you could also just use 'active.' Make the active region for the nmos the same size as the pmos you alread drew. Again we are going to draw a fet that is the minimum allowable size.

Gate Poly
Draw the gate poly as before.

Active Contacts
Place the contacts using 'cc'

Metal
Draw the metal1 layer surrounding the contacts.

N Select
Draw the n-select region to assign n-type doping to the active region.

Substrate Tap
In the case of the nmos we don't need to draw a well because the substrate is already p-type so the device is already isolated by a pn junction as long as this junction remains reverse-biased. We can ensure this by drawing a substrate tap to tie the substrate to ground. Draw the substrate tap just like the well tap, substituting 'pactive' for 'nactive' and 'pselect' for 'nselect.' Stretch the metal contact from the source to cover the substrate tap contact.

Here is what your nmos should look like.

Wiring up the Inverter

Now that we have drawn our transistors, we will want to connect them together to make the inverter.

First of all you will want to position your transistors properly. Select the entire nmos transistor and drag it below the pmos so that the gates are aligned horizontally and there is a gap of 1.2um between the nwell of the pmos and the pselect of the nmos. This is shown here:



Drawing Connections
First we will connect the outputs of the transistors to form the output net of the inverter circuit. Select 'metal1' from the LSW and draw a rectangle that connects the right contact of the pmos to the right contact of the nmos. Its alright if these rectangles overlap since they will be joined when the file gets converted to the mask set. If you want you can join them now by selecting them and using the 'merge' command or pressing shift-m. Sometimes this helps your layouts to look less cluttered. Only objects on the same layer will be merged.

While we have the metal1 layer selected lets draw the power rails. Draw a rectangle that is 3 lambda tall and the entire width of the both select regions (6.2um), spaced 3 lambda above the pmos active region. Repeat this below the nmos active region. These will be the supply rails for the circuit. Now connect these to the source/drain contacts of the transistors as shown here.



Note that we drew our supply rails the minimul allowable width (3 lambda.) This is not ususally advisable since these wires generally carry a lot of current. However, in this exercise we are trying to draw the smallest allowable inverter circuit, not necessarily one that will perform well for any given application. You will have to decide how wide you need to make your power rails when you draw the gates for your own project.

Now we will connect the gates and make a poly-metal1 contact to form the input of the circuit. Select 'poly' and connect the gates of the two transistors. Now we want to draw a square that is 4 lambda, abutting the connected gates. Place a 'cc' contact (2x2 lambda) in the center of this square. Finally draw a 'metal1' square covering the contact (4x4 lambda). Heres what you get:



Creating Pins
Now we need to add pins to get signals into and out of our circuit. Select 'metal1' from the LSW. Now select Create->Pin from the menu in Virtuoso. The create pin dialog box will open. We want to give out pins the same names we gave them in the other cell views (vdd, vss, in, out) so that they all match. First do vdd. Type in the pin name, keep the type as inputoutput. Click ok and draw a rectangle overlapping the high supply rail as shown below. Repeat for the other pins.



You are now finished with the layout for your inverter.

Design Rules Check

Before we proceed, we want to make sure we haven't made any errors in our layout. We will use the design rules checker (DRC) to ensure that we haven't violated any of the MOSIS design rules. This doesn't guarantee that the circuit will work properly; it only guarantees that the foundry can fabricate it as drawn.

Select Verify->DRC

The default options should work just fine. Click OK and the DRC will run. Check the CIW for the results. If there are no errors it will read

********* Summary of rule violations for cell "test layout" *********
Total errors found: 0

otherwise there will be a list of errors like this one:

4 (SCMOS Rule 6.5.b) active contact to active spacing: 1.50 um

The rule number will be listed along with a description, which is very helpful when troubleshooting. You can go to the Mosis rules website to get the details of the rule in question.

You are done with this section.

Part 7 - Layout Extraction

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Overview

In this module you will perform an extraction of your cell. This process will generate a detailed description of the circuit (netlist) that includes the parasitic resistances and capacitances associated with the individual transistors as well as the interconnections. This will allow a more realistic simulation than we we able to do using just the schematic, since it ignored everything except the behavior of the isolated transistors.

Extraction

Save your layout.

To begin extraction, select Verify->Extract

The extractor will pop-up. Click on 'Set Switches' and select Extract_parasitic_caps. If we didn't set this we would get the same result that we got using the schematic and this would be pointless. Since we don't have any instances of other cells we can leave the ectract method on 'flat.' Click OK and check the CIW for the results. This could take a few minutes.

You will see a list of the transistors and capacitors that the extractor identified. Check it out and see if it makes sense. Do you have the number of nmos and pmos that you expected?

Layout versus Schematic

Open the extracted cellview in Virtuoso. It will look similar to the layout except that only the pins will appear as solid rectangles. Also, you will see symbols representing the extracted nmos, pmos and capacitors.

Now we will compare the layout and the schematic to ensure that they are functionally equivalent circuits. Cadence has a tool that will compare the netlist generated by the extraction with a schematic.

Select Verify->LVS

The LVS window will open as well as an 'LVS Form Contents' window. Ensure that the box marked 'form contents' is checked in the second window. In the LVS window, ensure that both the schematic and extracted cells are listed correctly. The other defult options should be sufficient. Click Run. After a couple minutes you should get a messge that the job succeeded. This doesn't mean your netlists matched, only that the checker ran without error.
Click 'Output' to view the results.

The file should say that the netlists match. If not, you may need to change your layout to match your schematic, but first, you should check to ensure that the pin names match in both files as this is a common error.

Part 8 - Layout Simulation

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Overview

In this module you will simulate your inverter again, this time using the extracted layout. For the sake of time, we will just run a transient analysis. I'll trust that you know how to repeat the DC analysis that we did before. We're going to use a quick and dirty way of simulating our circuit without using a testbench circuit. This is not usually a good practice but is sometimes useful so I'll use this opportunity to show you how. The benefit of a testbench circuit is that you can set the load and see how your device would perform in a realistic situation. Also you are less likely to screw up your cells that way since you don't have to open them up, you just instance them in another schematic.

Running the Simulation

Open the analog environment directly from the extracted Cell View.

Select Setup->Environment. In the switch view list, add 'extracted' before 'schematic.' The simulator will search in this order and will stop when it encounters the Cell View 'extracted.'

Now select Setup->Stimulus->Edit Analog. Select 'graphical' and click OK. This window will appear:



The first source in the list is 'in.' Clikc the 'enabled' button, set the function to pulse. Set the Voltage 1 and Voltage 2 to 0 and 5 volts as before. Set the pulsewidth and period to 1ns and 2ns as before. You can also set a rise time, fall time and delay time if you wish. Click 'Change' to apply the changes. In the same way, set vdd to be a 5V dc source and vss to be a 0V dc source. Click OK.

Select transient analysis as before. Set the stop time to 10ns.

Select the outputs to be plotted as before.

Run the simulation. You should get this:

Part 9 (Appendix) - Verilog

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Overview

In this module you will extract a verilog netlist and use Verilog-XL to perform a digital simulation of your inverter. You may choose to use this type of simulation either before or after you do the layout of a cell. Beforehand, you may want to verify the correct operation of a newly designed schematic. If this circuit is large, the digital simulation may considerably faster than performing a full analog Spectre simulation of the circuit. Again, after layout, very large circuits may be very slow to simulate using Spectre. Once your circuit passes LVS, you can run the digital simulation on your schematic since it is equivalent to your layout.

Running Verilog XL.

Create a new Cell View called inv_vtest of type schematic. We are doing this because we will have to rename some of the pins to get verilog to work properly and we don't want to screw up our original schematic.

Create an instance of you inverter in the new cell. Create 4 inputOutput pins called in, out, vdd! and vss! and connect them to the four terminals of the inverter accordingly.



The '!' marks the pins as global nets and is necessary for Verilog, but not for Spectre. We purposely didn't want the supplies to be global nets in our schematic because I find that having to wire up the supplies in the schematic reminds me as I'm designing the circuit that I need to think about how these wires will be routed in the layout.

Check and save your design. Open Verilog XL by clicking Virtuoso->Tools->Simulation->Verilog XL

You will be prompted for a run directory. You can use the default or enter another directory if you wish. Click OK.

The Virtuoso Verilog Environment will open.

Creating the Netlist

Select Setup->Netlist

This will open the netlist option form. Ensure that the List "netlist these views" contains "functional" and "schematic." Click the 'more' button. Rename the Global Power Net and Global Ground Nets to match the names on your schematic (vdd!, vss!). Click OK.

Select Setup->Record Signals

Select "Design Selections" from drop-down menu. Then on your schematic highlight the wires or pins that you would like to record. Click OK.

Select Stimulus->Verilog

Tell the pop-up to create a new stimulus file for you. Select testfixture.verilog and click ok.

Now we are ready to generate a netlist for our schematic. Click the only button that isn't grayed out, or select simulation->start interactive. This will generate a Verilog netlist. The CIW window will tell you whether this was successful or not.

If it succeeded, click the continue button to run the simulation. This will not do anything particularly useful since you still have the default testfixture.verilog file.

Modifying the Stimulus File

We need to modify the stimulus to include our desired stimuli.

Use a text editor and open the file testfixture.verilog from the run directory. It will contain this:

// Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin io_cdsNet1 = 1'bz; io_cdsNet0 = 1'bz; io_in = 1'bz; io_out = 1'bz; end

Modify it like this.

// Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin io_cdsNet1 = 1'bz; io_cdsNet0 = 1'bz; io_in = 1'bz; io_out = 1'bz; #20 io_cdsNet1 = 1'b1; io_cdsNet0 = 1'b0; #10 io_in = 1'b1; #10 io_in = 1'b0; #10 io_in = 1'b1; #10 io_in = 1'b0; #30 io_in = 1'b1; end

#10 means to wait 10 times the global timestep. 1'b0 means the signal is a single bit and we want to set it to 0.

For more info on Verilog stimulus files see this link.

Save the file and close it.

Running the Simulation

In the Verilog window, select simulation->Start Interactive again. It will ask you if you want to regenerate the netlist. Say no since you haven't changed the schematic. Now click continue and it will run using your new testfixture.verilog. Click view waveforms at the bottom of the toolbar to open the waveform viewer.

Once the Simvision window opens, and sometimes this takes a while (I think it has to do with the network and the licensing but I'm not sure), it should automatically display the outputs that you selected. Check it out.